Search - gray code

[Communication-Mobile] lab24b

Description: 32qam modulation with gray code on Monte Carlo
Platform: | Size: 1024 | Author: yang | Hits:

Description: 格雷码生成对于给定的正整数n，格雷码为满足如下条件的一个编码序列： (1) 序列由2n个编码组成，每个编码都是长度为n的二进制位串。 (2) 序列中无相同的编码。 (3) 序列中位置相邻的两个编码恰有一位不同。 -Gray code generated for a given positive integer n, Gray code to meet the following conditions of a coding sequence: (1) coding sequence by the 2n months, each code is a length of n-bit binary string. (2) without the same sequence number. (3) the location of sequences adjacent to the two just have a different encoding.
Platform: | Size: 1024 | Author: Rei | Hits:

[VHDL-FPGA-Verilog] fifo

Description: 用双端口ram实现异步fifo，采用格雷码，避免产生毛刺。-Using dual-port ram realize asynchronous fifo, the use of Gray code, avoiding the production of burr.
Platform: | Size: 1024 | Author: shili | Hits:

[Other] Hanoi(gray)

Description: //使用gray code的解法 #include <iostream> #include <cmath> using namespace std #define ZERO 0 #define ONE 1 #define ODD 1 #define EVEN 0 #define RIGHT 1 #define LEFT 0 #define MAX 10-//Gray code to use the method# Include <iostream># Include <cmath> using namespace std# Define ZERO 0# Define ONE 1# Define ODD 1# Define EVEN 0# Define RIGHT 1# Define LEFT 0# Define MAX 10
Platform: | Size: 1024 | Author: Campbell | Hits:

[Special Effects] pipei

Description: .testpipei_1.m文件为基于灰度的模板匹配代码，仅为单独使用，不具有交互性 2.testpipei_2.m文件为基于灰度的快速模板匹配代码，仅为单独使用，不具有交互性 3.three.m为带有界面的演示程序，包含了上述两种算法，在MATLAB7.1中，在命令窗口下输入 edit three （three文件一定要在work文件夹下）回车后就可以进行使用了。 4.testpipei_1.m和testpipei_2.m的函数使用说明详细见各自的文件内 5.testpipei_1.m,testpiei_2.m,getOrder.m,gettezheng.m都为函数文件 three.m和three.fig共同为演示界面文件。-. testpipei_1.m file for the template matching based on gray code, only single use, non-interactive documents 2.testpipei_2.m fast gray-based template matching code, only single use, non-interactive 3. three.m for a demo program interface that contains the above two algorithms, in MATLAB7.1, in the command window, enter the edit three (three documents must be in the work folder) after carriage return can be used . 4.testpipei_1.m and testpipei_2.m a function of the use of a detailed description see the respective paper 5.testpipei_1.m, testpiei_2.m, getOrder.m, gettezheng.m document for function three.m and three.fig together for the presentation interface file.
Platform: | Size: 196608 | Author: 郭飞飞 | Hits:

[Embeded-SCM Develop] geryandbin

Description: 在fpga中实现的格雷码与二进制的相互转换-In the FPGA implementation of the Gray code and binary conversion
Platform: | Size: 1024 | Author: 王石子 | Hits:

[Other] p5

Description: Tutorial CODE conversors binary-gray and bcd-2-5-Tutorial CODE conversors binary-gray and bcd-2-5
Platform: | Size: 25600 | Author: lucas mg | Hits:

[Special Effects] ImageProcessing-source-code

Description: 负责图像处理的相关操作，如保存、图像关联操作等。功能包括：获取图片信息、缩放、色彩滤镜、亮度、反向、灰度、转换、裁贴、和插入文字、其它图片或几何图形。 Paint方法使用AutoScoolPosition属性发现滚动位置，使用AutoScrollMinSize属性进行设置。-Responsible for the relevant image processing operations, such as the preservation of image related operation. Features include: access to image information, zoom, color filters, brightness, reverse, gray, conversion, CD paste, and insert text, images or other geometric shapes. Paint ways to use attributes found Rolling AutoScoolPosition location, use AutoScrollMinSize attribute set.
Platform: | Size: 56320 | Author: 纪凤伟 | Hits:

[VHDL-FPGA-Verilog] fifo_ptrs_gray

Description: fifo pointers in verilog gray code utilization for synchronius
Platform: | Size: 3072 | Author: sljt | Hits:

[VHDL-FPGA-Verilog] dekoder

Description: dekoder code s Gray to cod „ 1 from 16”. This is program i VHDL-dekoder code s Gray to cod „ 1 from 16”. This is program i VHDL
Platform: | Size: 231424 | Author: adziolek | Hits:

[Other] Golay_coding

Description: 该程序实现的是一种完备格雷码的生成过程，Golay（23，12，7）码是典型的少数的完备码之一-The program implementation is a perfect Gray code generation process, Golay (23,12,7) code is a typical one of the few yards of the perfect code
Platform: | Size: 7168 | Author: 吕思达 | Hits:

[Data structs] gray

Description: Gray码是一个长度为2n的序列。序列中无相同元素，每个元素都是长度为n位的串，相邻元素恰好只有1位不同。用分治策略设计并实现一个算法对任意的n构造响应的Gray码。-Gray code is a sequence of length 2n. No similar sequence elements, each element is n-bit string length, the adjacent element is only a difference exactly. With sub-rule strategy was designed and implemented an algorithm for arbitrary n-constructed response Gray codes.
Platform: | Size: 1024 | Author: huzhaowei | Hits:

[Windows Develop] Gray

Description: 递归与分治演算Gray码，Gray码是一个长度为2N的序列-Recursive partition calculus with the Gray code, Gray code is a sequence of length 2N
Platform: | Size: 3072 | Author: 林子 | Hits:

[VHDL-FPGA-Verilog] binarytograyandgraytobinarycodeconverter

Description: this project is based on 4bit binary to gray and gray to binary code converter using vhdl.this is the 100 correct code,reference is taken from book digital electrionics written by anand kumar.please use quatrus to access this code.this code can be used for the final year project for engineering. Here dataflow techniques and behavioural techniques are used. - this project is based on 4bit binary to gray and gray to binary code converter using vhdl.this is the 100 correct code,reference is taken from book digital electrionics written by anand kumar.please use quatrus to access this code.this code can be used for the final year project for engineering. Here dataflow techniques and behavioural techniques are used.
Platform: | Size: 61440 | Author: jatab | Hits:

[VHDL-FPGA-Verilog] GrayCnt

Description: 格雷码计数器 VerilogHDL语言编写-Gray-code counter using VerilogHDL language
Platform: | Size: 8192 | Author: zy | Hits:

[Picture Viewer] Gray

Description: 进行Gray码的图像变化，思想是进行位操作，首先将原始图先的每一位取出来，然后将十进制转化位二进制，将其按位取出，进行变换，得到变换后图像的每一位的值，再进行组合即可-Gray code for the image change idea is to place operation, first the original plan to take out each and every first and then bit binary decimal conversion, be removed by bit, for transformation, transformed the image of each of value, then the combination can be
Platform: | Size: 1024 | Author: 方磊 | Hits:

[VHDL-FPGA-Verilog] vhdlcoder

Description: 本文件夹包含了16个VHDL 编程实例，仅供读者编程时学习参考。一、四位可预置75MHz -BCD码（加/减）计数显示器（ADD-SUB）。二、指示灯循环显示器（LED-CIRCLE) 三、七人表决器vote7 四、格雷码变换器graytobin 五、1位BCD码加法器bcdadder 六、四位全加器adder4 七、英语字母显示电路 alpher 八、74LS160计数器74ls160 九、可变步长加减计数器 multicount 十、可控脉冲发生器pluse 十一、正负脉宽数控调制信号发生器pluse width 十二、序列检测器string 十三、出租车计费器spend 十四、数字秒表selclk 十五、抢答器 first -This folder contains 16 examples of VHDL programming, only for readers to learn programming reference. 1, 4 Preset 75MHz-BCD code (plus/minus) count display (ADD-SUB). Second, light cycle display (LED-CIRCLE) 3, seven voting machines vote7 4, Gray code converter graytobin 5, a BCD code adder bcdadder six, four full adder adder4 seven or eight English letter display circuit alpher , 74LS160 counter 74ls160 9, variable-step addition and subtraction counters multicount 10, controllable pulse generator pluse 11, positive and negative pulse width modulation signal generator pluse width of NC 12, sequence detector string 13, a taxi billing spend 14 devices, digital stopwatch selclk 15, Responder first
Platform: | Size: 59392 | Author: 李磊 | Hits:

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